1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming substrates comprised of different semiconductor materials that may be used to manufacture various types of semiconductor devices and integrated circuits.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fin with inversion carriers, contributes to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as so-called III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation. However, the integration of such alternative materials on silicon substrates (the predominate substrates used in the industry) is a non-trivial matter due to, among other issues, the large difference in lattice constants between such alternative channel materials and silicon.
FIGS. 1A-1C depict illustrative examples of prior art substrates comprised of alternative channel semiconductor materials. One technique of forming such substrates, reflected in FIG. 1A, involves performing a blanket growth process to form a layer of the alternative channel material 14 above a silicon substrate 10. Due to the lattice constant mismatch between the silicon substrate 10 and the alternative channel material 14, this approach typically involves the formation of one or more strain relief buffer (SRB) layers 12 between the substrate 10 and the alternative channel material 14. The drawing on the left in FIG. 1A depicts the situation where a single SRB layer 12 may be formed above the substrate 10. Typically, such a single SRB layer would be relatively thick and the lattice constant of the SRB layer 12 would be different at the SRB/substrate interface and the SRB/channel material interface. The drawing on the right side of FIG. 1A depicts the situation where any number of multiple SRB layers may be positioned between the substrate 10 and the channel material 14. In the depicted example, there are two such illustrative SRB layers 12A, 12B. In a particular situation, the number of SRB sub-layers with each different lattice constant may be quite as high as 20 or 30. Here, for simplicity, we illustrate 2 layers. The SRB layers 12, 12A/B are typically comprised of a set of various materials that are epitaxially grown on top of each other so as to gradually change the lattice constant from the substrate material 10 more towards the lattice constant of the channel material 14, such that the top layer matches the lattice constant of the channel material 14 and is more relaxed and substantially defect-free. The purpose of the SRB layers 12, 12A/B is to provide a smoother, more gradual transition between the two mismatched materials 10, 14, with the ultimate goal being to produce relaxed and defect-free channel material with high charge carrier mobility properties. The structure depicted in FIG. 1A may be formed by epitaxially depositing the various material layers on and above the substrate 10.
In an alternative process, blanket III-V layers may also be formed on or above a silicon substrate by the use of well-known wafer bonding techniques. Using such techniques, one or more III-V layers are transferred from a donor substrate to a target substrate; similar to well-known SOI fabrication processes. FIG. 1B depicts an illustrative example of such a completed substrate wherein the channel material 14 is positioned on a layer of silicon dioxide 13 that was formed on the substrate 10. Using either technique, the substrate 10 remains covered by a layer of the alternative channel material 14. Thus, using this approach, it is difficult to incorporate multiple alternative channel materials on a single substrate that is suitable for use in CMOS applications wherein different type devices, i.e., N-type devices and P-type devices, are formed above a single substrate.
FIG. 1C reflects another technique of forming alternative channel materials that involves a confined growth type processing technique, generally known as aspect ratio trapping (ART). Under the ART approach, a trench 16, typically a high aspect ratio trench having an aspect ratio on the order of about 3:1-8:1, is formed in a dielectric layer 15 formed above a silicon substrate 10. Thereafter, the alternative channel material 14 is grown in the trench 16. Typically, the bottom of the trench 16 exposes the substrate material so as to allow for bottom-up epitaxial growth of the channel material 14. The sidewalls of the trench 16 are typically formed in the dielectric layer 15, e.g., silicon dioxide, so as to provide selectivity of epi growth from the bottom only and not from the sidewalls of the trench 16. The dielectric layer 15 may also serve electrical isolation purposes between devices. Due to the aspect ratio of the trench 16, and the nature in which defects within the alternative channel material 14 propagate upwards (at an angle of about 45°), most defects that originate from the bottom of the trench 16 will naturally stop at the sidewalls of the trench 16, at the dielectric layer 15. Thus, the upper portion of the alternative channel material 14 is expected to be substantially defect-free. Unfortunately, with some desirable alternative channel materials, such as III-V materials, it is very difficult to fill very high aspect ratio trenches 16 or trenches that are very narrow.
The present disclosure is directed to various methods of forming substrates comprised of different semiconductor materials that may be used to manufacture various types of semiconductor devices and integrated circuits that may solve or at least reduce one or more of the problems identified above.